| OBC-Laboratory |
|
For the development of the On-Board Computer (OBC) system of the Flying Laptop, one of the rooms at the IRS is dedicated as OBC-Laboratory. As the components of the OBC system are mainly developed and delivered by external partners, the focus of the development in the OBC-Lab lies on the development and implementation of the On-Board Software (OBSW) for the Flying Laptop.
The OBSW, written in C/C++, is based on an RTEMS kernel and will be built up on top of that. As the OBC processor is different from a common processor, the software cannot simply be built with a system compiler and run on the development machine but has to be tested on special development boards equipped with an IP core representing the architecture of the real OBC. Therefore, beside numerous development computers installed in the OBC-Lab, FPGA development boards are also present to allow reasonable testing. For the development of the OBSW, a SCRUM process has been determined to be followed during the development phase. This process dictates a two-weeks-period in which a certain number of features is supposed to be implemented. After this period, a fully implemented and tested revision of the S/W is to be released to improve the S/W step by step plus allow testing it by connecting it to the simulator in the MDVE. Here it can be seen whether the software does what it is supposed to do or behaves how it is supposed to behave for example in case of failures or malicious input or not. For smaller problems a daily fast-report-meeting is held. In the OBSW the device handler needed to communicate with the instruments (reaction wheel, magnetorquer,...) and sensors (sun sensor, temperature sensors,...) are included. They translate commands from the OBC to the devices in understandable form and translate reports from the devices to the OBC so as that the OBC can understand them. Every variable used in the OBSW is supposed to be stored in a main OBSW datapool. From there, the different controller for attitude control, thermal control, power control, communication and payload algorithms can get the requested input and write their results back to the datapool. For the occurrence of malfunctions of the devices or malicious out- or inputs a Failure detection, Isolation and Recovery (FDIR) function will be implemented to recover the satellite and regain a stable state. For the development of the OBSW, Ph.D. candidates of the IRS are in response of the process. Together with students (HiWi, Student/Diploma Thesis, Bachelor/Master Thesis) the framework of the OBSW is designed, the functions and features are determined and implemented and test procedures are developed and implemented to result in a reasonable OBSW for autonomous operation of the satellite in space. |









